Not Applicable.
1. Field of the Invention
The present invention is directed generally to a semiconductor memory device and, more particularly, to an equilibrate circuit for dynamic plate sensing semiconductor memories.
2. Description of the Background
In a conventional dynamic random access memory (DRAM) device each memory cell, or memory-bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digitline, or bitline, of the memory-device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the bitline and the capacitor.
The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as VCC/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the bitline. The capacitor stores a charge that, depending on whether the polarity of the voltage across the capacitor is positive or negative, represents either a logic high or a logic low value.
Memory devices are typically constructed with complementary bitlines of equal capacitance. Sense amplifiers are connected between the bitlines and operate to sense the differential voltage across the bitlines. Before a memory cell is selected for access, the complementary bitlines must be equilibrated to minimize the cell access time. Equilibration circuits typically short the complementary bitlines together, resulting in an equilibrate voltage equal to the voltage midpoint between the two equal capacitance and logically opposite bitlines.
In a dynamic plate-sensing memory device, each memory cell typically consists of a transistor and a capacitor. The transistor is connected to a bitline and the terminal of a capacitor. The other terminal of the capacitor is connected to a cell plateline. A wordline is connected to the gate terminal of the transistor. Thus, the capacitor is connected between the bitline and the plateline when the wordline is active.
Certain types of dynamic plate sensing memory devices, such as 6F2 dynamic plate sensing memory devices, do not have complementary bitline architectures. Thus, conventional techniques of equilibrating bitlines, such as that shown in Asakura, et al., xe2x80x9cCell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM""sxe2x80x9d, IEEE Journal of Solid-State Circuits, vol. 27, no. 4, April 1992, pp. 597-602, would be ineffective because such conventional techniques require complementary bitlines that can be shorted together to obtain the midpoint of the equal and opposite capacitances of the bitlines.
Thus, the need exists for an equilibrate circuit that is capable of equilibrating the bitlines and the platelines, which have unequal capacitances, of a dynamic plate sensing memory device which does not have a complementary bitline architecture.
The present invention, according to its broadest implementation, is directed to a circuit for equilibrating non-symmetric differential inputs of a memory device that require equilibration. The circuit comprises a first device for driving the plateline toward a predetermined voltage, a second device for driving the bitline toward the predetermined voltage, and a third device for connecting the bitline to the plateline.
The present invention also contemplates a semiconductor dynamic plate sensing memory device with a memory array, read and write circuits, and a plurality of equilibrate circuits. The equilibrate circuits comprise a first device for driving the plateline toward a predetermined voltage, a second device for driving the bitline toward the predetermined voltage, and a third device for connection the plateline to the bitline.
The present invention may also be a part of a complete memory device which itself may be a part of a system. The system may comprise a processor, a memory controller, a plurality of memory devices with equilibrate circuits, and two buses.
The present invention also contemplates a method for equilibrating a plateline and a bitline of a dynamic plate sensing memory device.
The present invention represents a substantial advance over prior equilibrate circuits. Because the present invention does not rely on complementary bitlines to equalize the bitlines, it may be incorporated in dynamic plate sensing memory devices that do not have complementary bitlines. This, and other advantages and benefits of the present invention, will become apparent from the Detailed Description of the Preferred Embodiments hereinbelow.